MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 556
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer:
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Serial Communication Controllers (SCCs)
7.10.21.11 TRANSPARENT EVENT REGISTER (SCCE). The SCCE is called the trans-
parent event register when the SCC is operating as a transparent controller. It is a 16-bit reg-
ister used to report events recognized by the transparent channel and to generate interrupts.
On recognition of an event, the transparent controller will set the corresponding bit in the
transparent event register. Interrupts generated by this register may be masked in the trans-
parent mask register.
The transparent event register is a memory-mapped register that may be read at any time.
A bit is reset by writing a one (writing a zero does not affect a bit’s value). More than one bit
may be reset at a time. All unmasked bits must be reset before the CP will negate the inter-
nal interrupt request signal. This register is cleared at reset.
Bits 15–13, 9–8, 6–5—Reserved
GLr—Glitch on Rx
GLt—Glitch on Tx
DCC—DPLL CS Changed
GRA—Graceful Stop Complete
TXE—Tx Error
RCH—Receive Character
BSY—Busy Condition
7-232
15
A clock glitch was detected by this SCC on the receive clock.
A clock glitch was detected by this SCC on the transmit clock.
The carrier sense status as generated by the DPLL has changed state. The real-time sta-
tus may be found in SCCS. This is not the CD pin status, which is reported elsewhere,
and is only valid when the DPLL is used.
A graceful stop, which was initiated by the GRACEFUL STOP TRANSMIT command, is
now complete. This bit is set as soon the transmitter has finished transmitting any frame
that was in progress when the command was issued. It will be set immediately if no frame
was in progress when the command was issued.
An error (CTS lost or underrun) occurred on the transmitter channel.
A byte or long word has been received and written to the buffer. This depends on the set-
ting of the RFW bit in the GSMR.
A byte/long-word was received and discarded due to lack of buffers. The receiver will re-
sume reception after an ENTER HUNT MODE command.
14
—
13
GLr
12
GLt
11
Freescale Semiconductor, Inc.
For More Information On This Product,
DCC
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
—
9
—
8
GRA
7
—
6
—
5
TXE
4
RCH
3
BSY
2
TX
1
RX
0
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