MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 358

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
IDMA Channels
7.6.4 IDMA Operation
Every IDMA operation involves the following steps: IDMA channel initialization, data trans-
fer, and block termination. In the initialization phase, the core (or external processor) loads
the registers with control information, initializes the IDMA BDs (if auto buffer or buffer chain-
ing is used), and then starts the channel. In the transfer phase, the IDMA accepts requests
for operand transfers and provides addressing and bus control for the transfers. The termi-
nation phase occurs when the operation is complete and the IDMA interrupts the core if
interrupts are enabled.
To initialize a block transfer operation, the user must initialize the IDMA registers. For the
auto buffer and buffer chaining modes, the IDMA BDs must be initialized with information
describing the data block, device type, request generation method, and other special control
options. See 7.6.2 IDMA Registers and 7.6.4.2.3 IDMA Commands (INIT_IDMA) for further
details.
7.6.4.1 SINGLE BUFFER. The single buffer mode is used to transfer only one buffer of
data. When the buffer has been completely transferred (transfer count exhausted or DONEx
is asserted), the IDMA channel operation is terminated, STR is cleared, and a maskable
interrupt is generated by the DONE bit in the CSR.
7.6.4.2 AUTO BUFFER AND BUFFER CHAINING. The auto buffer and the buffer chaining
modes are supported with the RISC controller by setting the RCI bit in the CMR. The host
processor should initialize the IDMA BD ring (see Figure 7-9) with the appropriate buffer
handling mode, source address, destination address, and block length. The user then sets
the STR bit in the CMR. All transfer modes described in 7.6.4.4.4 External Cycle Steal are
still valid. The function codes for the source and destination addresses are programmed as
described in 7.5.2.5 Timer Capture Registers (TCR1, TCR2, TCR3, TCR4).
7-34
MC68360 USER’S MANUAL
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