MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 931

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

APPENDIX D
MC68MH360 PRODUCT BRIEF
The MC68MH360 is a derivative of the MC68360 QUICC.
QUICC32.
The QUICC32 has some modifications in the Communication Processor Module (CPM)
hardware and a larger internal dual port RAM. These hardware changes in combination with
a new ROM based microcode, called QMC (QUICC Multichannel Controller), emulates up
to 32 HDLC channels within one SCC. The MH360 is ideal in primary rate ISDN applications
and interfaces directly to a E1/T1 line and is capable of terminating all time slots using HDLC
or transparent mode of operation. One of the time slot assigners (SI) is dedicated to the use
of the QMC. The SI transfers the whole frame or selected time slots to one SCC. All other
features remain unchanged and the QUICC32 is pin compatible with the other family mem-
bers.
A QUICC32 in non-QMC mode has exactly the same functionality as a standard MC68360
with the exception that the Centronics and BISYNC protocols have been removed on the
QUICC32 to create ROM space for the QMC protocol.
D.1 QUICC32 KEY FEATURES
The following list summarizes the key MC68MH360 QUICC32 features:
D.1.1 General
• Up to 32 Independent Communication Channels
• Arbitrary Mapping of Any of 0-31 Channels to Any of 0-31 TDM Time Slots
• Can Support Arbitrary Mapping of Any of 0-31 Channels to Any of 0-63 TDM Time Slots
• Independent Mapping for Receive/Transmit
• Supports Either QUICC Transparent or QUICC HDLC Protocols for Each Channel
• QUICC-Like Manner for Channel Programming and Parameter Passing
• Up to 64 DMA Channels with Linear Buffer Array
• Interrupt Circular Buffer with Programmable Size and Overflow Identification
• Global Loop Mode
• Individual Channel Loop Mode
• Programmable Frame Length (Via QUICC’s SI)
in Case of Common Rx & Tx Mapping
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
It is also known as the