MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 268

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM60)
6.8.1 MBAR in a Multiple QUICC System
The module base address register (MBAR) is used to configure the location of the QUICC's
block of on-chip RAM and registers. In a multiple QUICC system, a technique must be pro-
vided to allow multiple MBARs on multiple QUICCs to be programmed with unique values.
The QUICC has several provisions to support this.
First, any QUICC that is configured into slave mode with its global chip select disabled
(CONFIG pins = 110) automatically has its MBAR location changed from $0003FF00 to
$0003FF04. Second, the MBAR, newly located at address $0003FF04, can only be enabled
for access after a keyed write operation is performed (see Figure 6-9). The keyed write
allows the user to program the MBARs of multiple QUICC slaves without adding any exter-
nal glue logic.
6-24
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Figure 6-9. MBAR Access to a Multiple QUICC Slave System
When used in slave mode, the QUICC must be configured with
a 32-bit data bus.
Even without the use of the slave mode, another processor can
be granted access to the QUICC's on-chip peripherals by re-
questing the bus with the BR pin.
If the QUICC is configured into slave mode with its global chip
select enabled, the MBAR location does not change, and the
keyed write is not required. Thus, a single QUICC configured as
a slave to an MC68EC040 or MC68EC030 does not require a
keyed write for its MBAR.
If there are N QUICCs sharing a bus, N–1 QUICCs would nor-
mally have their CONFIG pins configured as 110.
DUAL-PORT
REGISTERS
INTERNAL
RAM
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
NOTES
MBARE
MBAR
MBAR SELECT BIT (BIT 31)
$0003FF04; FC = 111
$0003FF08; FC = 111
MBARE PIN