MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 31

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

SECTION 1
INTRODUCTION
The MC68360 QUad Integrated Communication Controller (QUICC
chip integrated microprocessor and peripheral combination that can be used in a variety of
controller applications. It particularly excels in communications activities. The QUICC (pro-
nounced “quick”) can be described as a next-generation MC68302 with higher performance
in all areas of device operation, increased flexibility, major extensions in capability, and
higher integration. The term "quad" comes from the fact that there are four serial communi-
cations controllers (SCCs) on the device; however, there are actually seven serial channels:
four SCCs, two serial management controllers (SMCs), and one serial peripheral interface
(SPI).
The purpose of this document is to describe the operation of all QUICC functionality.
Although this document has an overview of the CPU32+, the M68000PM/AD M68000 Fam-
ily Programmer's Reference Manual should be used in addition to this document. The
CPU32RM/AD, M68300 Family CPU32 Reference Manual, also provides information on the
CPU32.
1.1 QUICC KEY FEATURES
The following list summarizes the key MC68360 QUICC features:
• CPU32+ Processor (4.5 MIPS at 25 MHz)
• Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)
• Up to 32 Address Lines (At Least 28 Always Available)
• Complete Static Design (0–25-MHz Operation)
• Slave Mode To Disable CPU32+ (Allows Use with External Processors)
• Memory Controller (Eight Banks)
—32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32)
—Background Debug Mode
—Byte-Misaligned Addressing
—Multiple QUICCs Can Share One System Bus (One Master)
—MC68040 Companion Mode Allows QUICC To Be an MC68040 Companion
—Also Supports External MC68030-Type Bus Masters
—All QUICC Features Usable in Slave Mode
—Contains Complete Dynamic Random-Access Memory (DRAM) Controller
—Each Bank Can Be a Chip Select or Support a DRAM Bank
—Up to 15 Wait States
Chip and Intelligent Peripheral (22 MIPS at 25 MHz)
Freescale Semiconductor, Inc.
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For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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