MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 518

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
7.10.18.2.3 Delayed RTS Mode. Sometimes HDLC bus may be used in a configuration
having a local HDLC bus and a standard transmission line that is not an HDLC bus. Figure
7-58 illustrates such a case. The local HDLC bus controllers do not communicate with each
other, but with a station on the transmission line; yet the HDLC bus protocol is used to con-
trol the access to the transmission line. In such a case, the RTS pin may be used as follows.
Normally, the RTS pin goes active at the beginning of the first bit of the opening flag. Use of
RTS is not normally required in HDLC bus; however, a mode exists on the QUICC’s HDLC
bus that delays the RTS signal by one bit with respect to the data. This mode is selected
with the BRM bit in the PSMR.
The delayed RTS mode is useful when the HDLC bus is used to connect multiple local
nodes to a transmission line. If the transmission line driver has a one-bit delay, then the
delayed RTS line can be used to enable the output of the transmission line driver. The result
is that the transmission line bits always drive "clean" without any collisions occurring on
them. The RTS timing is shown in Figure 7-59.
7-194
NOTES:
TX
RX
1. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port.
2. The RTS pins of each HDLC bus controller are configured to delayed RTS mode.
Figure 7-58. HDLC Bus Transmission Line Configuration
(1-BIT DELAY)
LINE
DRIVER
EN
Freescale Semiconductor, Inc.
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RTS
RXD
CONTROLLER
HDLC BUS
LOCAL HDLC BUS
TXD
A
CTS
RTS
RXD
CONTROLLER
HDLC BUS
TXD
B
CTS
R
+5