MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 757

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Applications
9.4.1.13 DOUBLE BUS FAULT. In MC68040 companion mode, the QUICC double bus fault
monitor is not operational.
9.4.1.14 JTAG AND THREE-STATE. Both the MC68EC040 and the QUICC provide JTAG
test access ports, commonly known as JTAG. This interface uses five pins: TMS, TDI, TDO,
TCK, and TRST. TMS and TDI are left unconnected because they have internal pullups. The
JTAG ports of both parts are disabled in this application; however, the capability could be
easily added.
When the QUICC is in master mode, it provides a TRIS pin that allows all outputs on the
device to be three-stated. In slave mode, this feature is not available since the QUICC is a
peripheral of the system. Thus, the transfer start (TS) pin is available instead of the TRIS pin
and does not conflict with it.
9.4.1.15 QUICC SERIAL PORTS. The functions on QUICC parallel I/O ports A, B, and C
may be used as desired in this application and have no bearing on the MC68EC040 inter-
face. However, any unused parallel I/O pins should be configured as outputs so they are not
left floating.
9.4.2 Memory Interfaces
In this application, a number of memory arrays have been developed for EPROM, burst
EPROM, flash EPROM, EEPROM, SRAM, burst SRAM, and DRAM. Each memory inter-
face can be attached to the system bus as desired.
One issue not discussed is the decision of whether external buffers are needed on the sys-
tem bus. This issue depends on the number of memory arrays used in the design and pos-
sibly the layout (i.e., capacitance) of the system bus.
Another issue left to the user is the number of wait states used with each memory system.
This depends on the memory speed, whether external buffers are used, and the loading on
the system bus pins. (The QUICC provides capacitance de-rating figures to calculate the
effect of more or less capacitance on the AC Timing Specifications.)
9.4.2.1 QUICC MEMORY INTERFACE PINS. In this design, a number of QUICC pins are
available to the memory arrays (see Figure 9-8). These pins are active, regardless of
whether the bus cycle was originated by the MC68EC040 or by one of the QUICC DMA
cycles. The QUICC detects the MC68EC040 bus cycle by the TS pin. If the QUICC gener-
ates the bus cycle, the QUICC asserts the AS pin.
Eight CSx or RASx pins are available in the system. In this design, CS0 is used for any of
the EPROM arrays since it is the global (boot) chip select. RAS1 is used for the DRAM
arrays because of its double-drive capability. CS2/RAS2 is not used in the design and is
available for other purposes, such as a second DRAM bank. CS3 is for SRAM arrays; CS4
is for EEPROM. CS5, CS6, and CS7 are unused.
In this design, it is assumed that the full 32-bit capability of the MC68EC040 is used; thus,
all memory arrays are 32 bits wide. (The only exception to this is the EEPROM, which is han-
MC68360 USER’S MANUAL
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