MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 348

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
IDMA Channels
caded mode.
7.6 IDMA CHANNELS
The QUICC includes a number of DMA channels, including 14 SDMA channels for the four
SCCs, two SMCs, and SPI and two general-purpose IDMA controllers. The SDMA channels
are discussed in 7.7 SDMA Channels. The IDMA channels are discussed in the following
paragraphs.
The two general-purpose IDMA controllers can operate in different modes of data transfer
as programmed by the user. The IDMA can transfer data between any combination of mem-
ory and I/O. In addition, data may be transferred in either byte, word, or long-word quantities,
and the source and destination addresses may be either odd or even. The most efficient
packing algorithms are used in the IDMA transfers. The single address mode gives the high-
est performance, allowing data to be transferred between memory and a peripheral in a sin-
gle bus cycle. The chip-select and wait-state generation logic on the QUICC may be used
with the IDMA.
The IDMA supports three buffer handling modes: single buffer, auto buffer, and buffer chain-
ing. Single buffer mode is that of the traditional DMA controller. The auto buffer mode allows
blocks of data to be repeatedly moved from one location to another without user interven-
tion. The buffer chaining mode allows a chain of blocks to be moved. The user specifies the
data movement using buffer descriptors that are similar to those used by an SCC. These
buffer descriptions reside in the dual-port RAM.
If the single buffer mode of the IDMA is used, programming the IDMA is very similar
(although not exactly software compatible) to that of the IDMA on the MC68302 or the DMA
controller on the MC68340. The auto buffer and buffer chaining modes, however, are not
available on those devices, and the single address mode is not available on the MC68302.
The maximum transfer rate of the IDMA is 50 Mbyte/sec. This assumes a 32-bit data transfer
from memory to peripheral using fast termination (2 clocks per bus cycle) timing and single
address mode: (4 Bytes
25 MHz Clocks/sec)/(2 Clocks per Transfer) = 50 Mbyte/sec.
The maximum transfer rate of the IDMA in dual address mode is 25 Mbyte/sec. This
assumes a 32-bit source and destination, fast termination (2 clocks per bus cycle) timing,
and two bus cycles for each transfer: (4 Bytes 25 MHz Clocks/sec)/(4 Clocks per Transfer)
= 25 Mbyte/sec.
The IDMA controller block diagram is shown in Figure 7-8.
7-24
MC68360 USER’S MANUAL
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