MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 368

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

IDMA Channels
IMB bus masters request bus ownership on a per-cycle basis. Thus, on each bus cycle, the
IMB is given to the highest priority bus master requesting the bus. External bus masters may
also request the bus and obtain priority over the internal bus masters.
In addition, on the QUICC, interrupts may take priority over bus masters. Thus, another con-
dition for the IDMA to obtain the bus is for the interrupt service level on the IMB to be less
than or equal to the interrupt service mask (ISM bits) in the ICCR.
If the CPU32+ is enabled, the IDMA bus arbitration sequence is like that shown in Figure 7-
12. The BR, BG, and BGACK signals are not affected during the arbitration sequence. The
only external indication of an IDMA bus request is the bus clear out (BCLRO) pin. BCLRO
is only available externally if programmed in the SIM60 port E pin assignment register. Addi-
tionally, BCLRO is only asserted if the IDMA ID for that channel is greater than the value
programmed into the BCLROID2-BCLROID0 bits in the SIM60 module configuration regis-
ter. BCLRO can be used to clear off an external bus master from the external bus, if desired.
For instance, BCLRO can be connected through logic to the external master’s HALT signal,
and then negated externally when the external master’s AS signal is negated. BCLRO is
negated during S2 of the final IDMA bus cycle before it relinquishes the bus.
7-44
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
NOTES:
Figure 7-12. IDMA Bus Arbitration (Normal Operation)
DSACKx
BCLRO
CLKO1
(INPUT)
(INPUT)
DACKx
DREQx
BGACK
1. The BCLRO signal is only asserted if the IDMA bus arbitration ID is greater than
2. Note that the BR, BG, and BGACK signals are not affected by the IDMA bus arbi-
(I/O)
(I/O)
AS
BR
BG
the BCLROID2–BCLROID0 bits in the SIM60 module configuration register.
tration process if the CPU32+ is enabled.
S0
Freescale Semiconductor, Inc.
For More Information On This Product,
DREQ SAMPLED
LOW
OTHER CYCLE
S2
MC68360 USER’S MANUAL
Go to: www.freescale.com
S4
S0
IDMA READ
S2
S4
S0
IDMA WRITE
S2
S4
S0