MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 568

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

RSTRT
RRJCT
Serial Communication Controllers (SCCs)
The CAM control logic uses RSTRT, in combination with the RXD and RCLK signals, to
store the destination address, source address, etc. and generate writes to the CAM for
address recognition. In addition, the RENA signal supplied from the EEST may be used to
abort the comparison if a collision occurs on the receive frame.
After the comparison occurs, the CAM control logic asserts the receive reject (RRJCT) pin,
if the current receive frame should be rejected. The QUICC Ethernet controller will then
immediately stop writing data to system memory and will reuse the buffer(s) for the next
frame. If the CAM wishes to accept the frame, the CAM control logic does nothing (RRJCT
is not asserted). If RRJCT is asserted, it must be asserted prior to the end of the receive
frame.
7-244
RXD
NOTE: The receive data is sent directly from the EEST serial interface to the CAM using RXD and RCLK. RSTRT is asserted
at the beginning of the destination address. RRJCT should be asserted during the frame to cause the frame to be rejected.
The system bus is used for CAM initialization and maintenance.
PREAMBLE
7 BYTES
SYSTEM BUS
ADDRESS BIT FOR A DURATION OF ONE
ASSERTED ON SECOND DESTINATION
Figure 7-68. QUICC Ethernet Serial CAM Interface
DELIMITER
1 BYTE
FRAME
START
Freescale Semiconductor, Inc.
BIT TIME.
SDACK2–SDACK1
For More Information On This Product,
6 BYTES
QUICC
ADDR.
DEST.
SCC
PARALLEL I/O
TCLK (CLKx)
RCLK (CLKx)
FRAME TAG
TENA (RTS)
CLSN (CTS)
OPTIONAL
RENA (CD)
PB15–PB8
MC68360 USER’S MANUAL
BYTE
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RSTRT
RRJCT
RxD
TxD
6 BYTES
SOURCE
ADDR.
SHIFT REGISTER
CAM CONTROL
2 BYTES
LENGTH
TYPE/
AND
FRAME REJECTED IF ASSERTED DURING FRAME RECEPTION.
RX
RENA
RCLK
CLSN
LOOP
TX
TENA
TCLK
FURTHER TRANSMISSIONS ON SYSTEM BUS CEASE, AND
MC68160
EEST
46–1500 BYTES
BUFFER DESCRIPTORS ARE REUSED.
DATA
CAM
TO MEDIA
SEQUENCE
4 BYTES
FRAME
CHECK