MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 85

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Table 4-5 lists the bytes required on the data bus for read cycles. The entries shown as OPx
are portions of the requested operand that are read during that bus cycle and are defined
by SIZ0, SIZ1, A0, and A1 for the bus cycle. Bytes labeled x are “don’t cares” and are not
required during that read cycle.
Table 4-6 lists the combinations of SIZ0, SIZ1, A0, and A1 and the corresponding pattern of
the data transfer for write cycles from the internal multiplexer of the QUICC to the external
data bus. Bytes labeled x are “don't care.”
Figure 4-4 shows the transfer of a long-word operand to a word port. In the first bus cycle,
the QUICC places the four operand bytes on the external bus. Since the address is long-
word aligned in this example, the multiplexer follows the pattern in the entry of Table 4-6 cor-
responding to SIZ0, SIZ1, A0, A1 = 0000. The port latches the data on bits D16–D31 of the
data bus, asserts DSACK1 (DSACK0 remains negated), and the QUICC terminates the bus
cycle. It then starts a new bus cycle with SIZ0, SIZ1, A0, A1 = 1010 to transfer the remaining
Transfer
3 Bytes
Word
Word
Long
Size
Byte
SIZ1 SIZ0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
Size
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
Table 4-5. Data Bus Requirements for Read Cycles
Address
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Freescale Semiconductor, Inc.
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
For More Information On This Product,
Table 4-4. Address Offset Encoding
D31:D24 D23:D16 D15:D8 D7:D0 D31:D24 D23:D16
A1
0
0
1
1
OP3
OP2
OP1
OP0
External Data Bytes Required
x
x
x
x
x
x
x
x
x
x
x
x
MC68360 USER’S MANUAL
Go to: www.freescale.com
Long-Word Port
OP3
OP3
OP2
OP2
OP1
OP1
OP0
x
x
x
x
x
x
x
x
x
A0
0
1
0
1
OP3
OP3
OP2
OP3
OP2
OP1
OP2
OP1
OP0
x
x
x
x
x
x
x
OP3
OP3
OP2
OP3
OP2
OP1
OP3
OP2
OP1
OP0
x
x
x
x
x
x
+2 Bytes
+3 Bytes
+0 Byte
+1 Byte
Offset
Data Bytes Required
Word Port External
OP3
OP3
OP2
OP2
OP1
OP1
OP0
OP0
x
x
x
x
x
x
x
x
OP3
OP3
OP3
OP2
OP3
OP2
OP2
OP1
OP2
OP1
OP1
OP0
OP1
OP0
x
x
Bytes Required
External Data
Bus Operation
Byte Port
D31:D24
OP3
OP3
OP3
OP3
OP2
OP2
OP2
OP2
OP1
OP1
OP1
OP1
OP0
OP0
OP0
OP0