MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 86

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bus Operation
16 bits. SIZ0 and SIZ1 indicate that a word remains to be transferred; A0 and A1 indicate
that the word corresponds to an offset of two from the base address. The multiplexer follows
the pattern corresponding to this configuration of the size and address signals and places
the two least significant bytes of the long word on the word portion of the bus (D16–D31).
The bus cycle transfers the remaining bytes to the word-size port. Figure 4-5 shows the tim-
ing of the bus transfer signals for this operation.
4-10
Table 4-6. QUICC Internal to External Data Bus Multiplexer—Write Cycle
Byte
Word
3 Bytes
Long Word
Transfer Size
31
D31
Figure 4-4. Example of Long-Word Transfer to Word Port
0P0
MSB
0P0
0P2
WORD MEMORY
SIZ1
DATA BUS
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
Freescale Semiconductor, Inc.
Size
For More Information On This Product,
SIZ0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
LSB
0P3
0P1
0P1
LONG-WORD OPERAND
MC68360 USER’S MANUAL
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A1
D16
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Address
SIZ1
0
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0P2
SIZ0
0
0
MC68360
D31:D24
OP3
OP3
OP3
OP3
OP2
OP2
OP2
OP2
OP1
OP1
OP1
OP1
OP0
OP0
OP0
OP0
A1
External Data Bus Connection
1
0
D23:D16
0P3
A0
0
0
OP3
OP3
OP2
OP3
OP2
OP1
OP2
OP3
OP2
OP1
OP0
OP1
OP0
x
x
x
DSACK1
0
MEMORY CONTROL
L
L
D15:D8
OP3
OP3
OP2
OP3
OP2
OP1
OP2
OP2
OP1
OP0
x
x
x
x
x
x
DSACK0
H
H
D7:D0
OP3
OP3
OP2
OP3
OP2
OP1
OP3
OP2
OP1
OP0
x
x
x
x
x
x