MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 655

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.12.8 SPI Interrupt Handling
The following list describes what would normally occur within an interrupt handler for the
SPI.
7.13 PARALLEL INTERFACE PORT (PIP)
The PIP is a function of the CPM that allows data to be transferred to and from the QUICC
over 8 or 16 parallel data pins. The pins of the PIP are multiplexed with the 18-bit port B par-
allel I/O port. The PIP supports the Centronics interface and a fast parallel connection
between QUICCs. When the PIP is used, the SMC2 channel is not available.
7.13.1 PIP Key Features
The PIP contains the following key features:
12. Write $0170 to SPMODE to enable normal operation (not loopback), master
13. Set the STR bit in the SPCOM to enable the SPI to be ready once the master
1. Once an interrupt occurs, the SPIE should be read by the user to see which sources
2. Process the Tx BD to reuse it and the Rx BD to extract the data from it. To transmit
3. Clear the SPI bit in the CISR.
4. Execute the RTE instruction.
• 18 General-Purpose I/O Pins
• Three Handshake Modes
• Programmable Handshake Timing Attributes
• Supports Centronics and Receiver/Transmitter Interface
• Allows Bidirectional Centronics (P1284) Operation To Be Implemented
• Supports Fast Connection Between QUICCs
• Can Be Controlled by the CPU32+ Core or by the CPM RISC
CICR should also be initialized.)
mode, SPI enabled, and 8-bit characters. The SPI baud rate generator speed is
ignored because the SPI is in slave mode.
begins the transfer.
have caused interrupts. The SPIE bits would normally be cleared at this time.
another buffer, simply set the Tx BD R-bit, the Rx BD E-bit, and the STR bit in SPCOM.
If the master transmits 3 bytes and negates the SPISEL pin, the
Rx BD will be closed, but the Tx BD will remain open. If the mas-
ter transmits 5 or more bytes, the Tx BD will be closed after the
5th byte. If the master transmits 16 bytes and negates the
SPISEL pin, the Rx BD will be closed with no errors, and no out-
of-buffers error will occur. If the master transmits more than 16
bytes, the Rx BD will be closed (completely full), and the out-of-
buffers error will occur after the 17th byte is received.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Parallel Interface Port (PIP)