MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 117

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

interrupt acknowledge cycle internally, the spurious interrupt monitor generates an internal
bus error signal to terminate the vector acquisition. The QUICC automatically generates the
spurious interrupt vector number, 24, instead of the interrupt vector number in this case.
When an external device does not respond to an interrupt acknowledge cycle with AVEC or
DSACKx, a bus monitor must assert BERR, which results in the CPU32+ taking the spurious
interrupt vector. If HALT is also asserted, the QUICC retries the interrupt acknowledge cycle
instead of using the spurious interrupt vector.
4.5 BUS EXCEPTION CONTROL CYCLES
The bus architecture requires assertion of DSACKx from an external device to signal that a
bus cycle is complete. Neither DSACKx nor AVEC is asserted in the following cases:
The QUICC provides BERR when no device responds by asserting DSACKx/AVEC within
an appropriate period of time after the QUICC asserts AS. This mechanism allows the cycle
to terminate and the QUICC to enter exception processing for the error condition. HALT is
also used for bus exception control. This signal can be asserted by an external device for
debugging purposes to cause single bus cycle operation or, in combination with BERR, a
retry of a bus cycle in error. To properly control termination of a bus cycle for a retry or a bus
error condition, DSACKx, BERR, and HALT can be asserted and negated with the rising
edge of the QUICC clock. This assures that when two signals are asserted simultaneously,
the required setup and hold time for both is met for the same falling edge of the QUICC
clock. This or an equivalent precaution should be designed into the external circuitry to pro-
vide these signals. Alternatively, the internal bus monitor could be used. The acceptable bus
cycle terminations for asynchronous cycles are summarized in relation to DSACKx assertion
as follows (case numbers refer to Table 4-8):
Table 4-8 shows various combinations of control signal sequences and the resulting bus
cycle terminations. To ensure predictable operation, BERR and HALT should be negated
according to the specifications in Section 10 Electrical Characteristics. DSACKx, BERR, and
HALT may be negated after AS. If DSACKx or BERR remain asserted into S2 of the next
bus cycle, that cycle may be terminated prematurely.
1. DSACKx in fast-termination cycles.
2. AVEC when programmed to respond internally.
3. The external device does not respond.
4. Various other application-dependent errors occur.
1. Normal Termination: DSACKx is asserted; BERR and HALT remain negated (case 1).
2. Halt Termination: HALT is asserted at the same time or before DSACKx, and BERR
3. Bus Error Termination: BERR is asserted in lieu of, at the same time, or before
4. Retry Termination: HALT and BERR are asserted in lieu of, at the same time, or before
remains negated (case 2).
DSACKx (case 3) or after DSACKx (case 4), and HALT remains negated; BERR is ne-
gated at the same time or after DSACKx.
DSACKx (case 5) or after DSACKx (case 6); BERR is negated at the same time or af-
ter DSACKx, and HALT may be negated at the same time or after BERR.
Freescale Semiconductor, Inc.
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MC68360 USER’S MANUAL
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Bus Operation