MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 572

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
C_PRES. For the 32-bit CRC-CCITT, C_PRES should be initialized with $FFFFFFFF.
C_MASK. For the 32-bit CRC-CCITT, C_MASK sh ould be initialized with $DEBB20E3.
CRCEC, ALEC, and DISFC. These 32-bit (modulo 2
They may be initialized by the user while the channel is disabled. CRCEC is incremented
for each received frame with a CRC error, except it does not includes frames not addressed
to the user, frames received in the out-of-buffers condition, frames with overrun errors, or
frames with alignment errors. ALEC is incremented for frames received with dribbling bits,
but does not includes frames not addressed to the user, frames received in the out-of-buff-
ers condition, or frames with overrun errors. DISFC is incremented for frames discarded
because of the out-of-buffers condition or an overrun error. The CRC does not have to be
correct for this counter to be incremented.
PADS. Into this 16-bit register the user writes the pattern of the pad characters that should
be sent when short frame padding is implemented. The byte pattern written to the register
may be any value, but both the high and low bytes should be the same.
RET_Lim. The user writes the number of retries that should be made to transmit a frame into
this 16-bit register. This value is typically 15 decimal. If the frame is not transmitted after this
limit is reached, an interrupt may be generated. RET_cnt is a temporary down-counter used
to count the number of retries made.
MFLR. The Ethernet controller checks the length of an incoming Ethernet frame against the
user-defined value given in this 16-bit register. Typically this register is set to 1518 decimal.
If this limit is exceeded, the remainder of the incoming frame is discarded, and the LG (Rx
frame too long) bit is set in the last Rx BD belonging to that frame. The Ethernet controller
will report the frame status and the frame length in the last Rx BD.
MFLR is defined as all the in-frame bytes between the start frame delimiter and the end of
the frame (destination address, source address, length, LLC data, PAD, and FCS).
DMA_cnt is a temporary down-counter used to track the frame length.
MINFLR. The Ethernet controller checks the length of an incoming Ethernet frame against
the user-defined value given in this 16-bit register. Typically this register is set to 64 decimal.
If the received frame length is less than the register value, then this frame is discarded
unless the RSH (receive short frames) bit in the PSMR is set. If RSH is set, then the SH (Rx
frame too short) bit is set in the last Rx BD belonging to that frame. For transmit operation,
if the frame is too short, the Ethernet controller will add PADs to the transmitted frame
7-248
SCC Base + 9E
SCC Base + A0
SCC Base + A2
NOTE:
1. The boldfaced items should be initialized by the user.
2. The address should be wrtten in little endian, not Motorola big endian format (i.e., physical address
112233445566 should be written PADDR1_L= 6655, PADDR1_M=4433, PADDR1_H=2211.
Table 7-11. Ethernet-Specific Parameters
TADDR_M
TADDR_H
TADDR_L
Freescale Semiconductor, Inc.
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MC68360 USER’S MANUAL
Go to: www.freescale.com
Word
Word
Word
Temp Address (LSB)
Temp Address
Temp Address (MSB)
32
) counters are maintained by the CP.
2