MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 344

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Timers
When working in the cascaded mode, the cascaded TRR, TCR, and TCN should always be
referenced with 32-bit bus cycles.
7.5.2.2 TIMER GLOBAL CONFIGURATION REGISTER (TGCR). The TGCR is a 16-bit,
memory-mapped, read/write register that contains configuration parameters used by all four
timers. It allows starting and stopping any number of timers simultaneously if one bus cycle
is used to access TGCR. The TGCR is cleared by reset.
CAS4—Cascade Timers
CAS2—Cascade Timers
FRZ—Freeze
STP —Stop Timer
RST—Reset Timer
GM2—Gate Mode for Pin 2
7-20
CAS4
15
This bit is only valid if the gate function is enabled in TMR3 or TMR4.
0 = Normal Operation.
1 = Timers 3 and 4 are cascaded to form a 32-bit timer.
0 = Normal Operation.
1 = Timers 1 and 2 are cascaded to form a 32-bit timer.
0 = The corresponding timer ignores the FREEZE pin.
1 = Halt the corresponding timer if the FREEZE pin is asserted. (The FREEZE pin is
0 = Normal operation.
1 = Reduce power consumption of the timer. This bit stops all clocks to the timer, ex-
0 = Reset the corresponding timer (a software reset is identical to an external reset).
1 = Enable the corresponding timer if the STP bit is cleared.
0 = Restart gate mode. The TGATE2 pin is used to enable/disable the count. The fall-
1 = Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2
FRZ4
14
asserted in background debug mode when the CPU32+ is enabled.)
cept the clock from the IMB interface, which allows the user to read and write timer
registers. The clocks to the timer remain stopped until the user clears this bit or a
hardware reset occurs.
ing edge of TGATE2 enables and restarts the count, and the rising edge of
TGATE2 disables the count.
does not restart the count value in TCN.
STP4
13
RST4
12
GM2
11
Freescale Semiconductor, Inc.
For More Information On This Product,
FRZ3
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
STP3
9
RST3
8
CAS2
7
FRZ2
6
STP2
5
RST2
4
GM1
3
FRZ1
2
STP1
1
RST1
0