R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 95

IC R8C/23 MCU FLASH 48-LQFP

R5F21238DFP#U0

Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Datasheets

Specifications of R5F21238DFP#U0

Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 10.2
System Clock Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
0
1.
2.
3.
4.
5.
Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the CM0 register.
The CM05 bit is to stop the XIN clock w hen the high-speed on-chip oscillator mode, low -speed on-chip oscillator
mode is selected. Do not use this bit for w hether the XIN clock is stopped. To stop the XIN clock, set the bits in the
follow ing orders:
(a) Set the OCD0 and OCD1 bits in the OCD register to 00b.
(b) Set the OCD2 bit to 1 (selects on-chip oscillator clock).
During external clock input, only the clock oscillation buffer is turned off and clock input is acknow ledged.
P4_6 and P4_7 can be used as input ports w hen the CM05 bit is set to 1 (XIN clock stops) and the CM13 bit in the
CM1 register is set to 0 (P4_6, P4_7).
When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
0 1
CM0 Register
0 0
Bit Symbol
(b1-b0)
Symbol
CM02
CM05
CM06
Page 73 of 501
CM0
(b3)
(b4)
(b7)
Reserved bits
WAIT peripheral function clock stop
bit
Reserved bit
Reserved bit
XIN clock (XIN-XOUT) stop bit
System clock division select bit 0
Reserved bit
(1)
Address
Bit Name
0006h
(2,4)
(5)
Set to 0
0 : Peripheral function clock does not stop
1 : Peripheral function clock stops in w ait
Set to 1
Set to 0
0 : XIN clock oscillates
1 : XIN clock stops
0 : Enables CM16, CM17
1 : Divide-by-8 mode
Set to 0
in w ait mode
mode
After Reset
01101000b
Function
(3)
10. Clock Generation Circuit
RW
RW
RW
RW
RW
RW
RW
RW

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