R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 121

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 12.2
12.1.5
Table 12.1
NOTE:
Undefined Instruction 0FFDCh to 0FFDFh
Overflow
BRK Instruction
Address Match
Single Step
Watchdog Timer
Oscillation Stop
Detection
Voltage Monitor 2
Address Break
(Reserved)
Reset
12.1.5.1
1. Do not use the single-step interrupt. For development tools only.
Interrupt Source
There are 4 bytes in one vector. Set the starting address of interrupt routine in each vector table. When an
interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.
Figure 12.2 shows the Interrupt Vector.
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh.
Table 12.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code
check function. For details, refer to 20.3 Functions to Prevent Rewriting of Flash Memory.
Interrupts and Interrupt Vector
(1)
Fixed Vector Tables
Interrupt Vector
Fixed Vector Tables
(1)
Vector address (H)
Vector address (L)
Page 99 of 501
0FFE0h to 0FFE3h
0FFE4h to 0FFE7h
0FFE8h to 0FFEBh
0FFECh to 0FFEFh
0FFF0h to 0FFF3h
0FFF4h to 0FFF7h
0FFF8h to 0FFFBh
0FFFCh to 0FFFFh
Address (L) to (H)
Vector Addresses
MSB
0 0 0 0
0 0 0 0
Interrupt on UND
If the content of address
instruction
Interrupt on INTO
instruction
0FFE7h is FFh, program
execution starts from the
address shown by the
vector in the relocatable
vector table.
Low address
Mid address
Remarks
High address
0 0 0 0
R8C/Tiny Series software
manual
12.5 Address Match
13. Watchdog Timer
10. Clock Generation Circuit
6. Voltage Detection Circuit
5. Resets
LSB
Interrupt
Reference
12. Interrupts