R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 85

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Table 7.28
X: 0 or 1
NOTE:
Table 7.29
X: 0 or 1
NOTE:
Table 7.30
X: 0 or 1
NOTES:
Table 7.31
X: 0 or 1
NOTES:
Register
Register
Setting
Setting
Register
Register
value
value
Setting
Setting
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the SOOS bit in the SSMR2 register to 1 when this pin functions as output.
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.
value
value
Bit
Bit
Bit
Bit
PD3_3
PD3_4
PD3_1
PD3
PD3
PD3
Port P3_0/TRAO
Port P3_1/TRBO
Port P3_3/SSI
Port P3_4/SDA/SCS
0
0
1
1
X
X
0
0
1
1
X
X
X
PD3_0
0
1
X
X
PD3
X
0
1
Clock Synchronous Serial I/O with Chip Select
CSS1
SSI output control
(Refer to Table 16.4 Association between
Page 63 of 501
X
0
0
0
0
0
1
1
Communication Modes and I/O Pins.)
TMOD1
SSMR2
0
0
Other than 00b
X
X
0
0
0
1
CSS0
TRAIOC
TRBMR
TOENA
X
0
0
0
0
1
0
1
01b
0
0
1
TMOD0
IICSEL
PMR
0
0
X
X
0
0
0
0
1
SSI input control
Input port
Output port
TRAO output
ICCR1
ICE
X
X
0
0
1
0
X
X
X
X
0
0
1
TRBIOC
TOCNT
(1)
X
X
1
0
Input port
Output port
SCS input
SCS output
SDA input/output
Input port
Output port
TRBO output
IICSEL
PMR
(1)
0
1
0
1
0
0
(2)
(2)
(1)
Input port
Output port
SSI input
SSI output
Function
Function
(1)
(2)
(2)
Function
7. Programmable I/O Ports
Function