R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 352
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.29
Slave Address Register
IIC Bus Transmit Data Register
b7 b6
b7
b5
b4
b3 b2
Registers SAR and ICDRT
b1
b0
b0
Store transmit data
When detecting that the ICDRS register is empty, the stored transmit data is transferred to the
ICDRS register and the starts transmit data.
When the next transmit data is w ritten to the ICDRT register during transmitting the data of the
ICDRS register, continuous transmit is enabled. When the MLS bit in the ICMR register is set to
1 (data transferred by LSB-first) and after the data is w ritten to the ICDRT register, the MSB
and LSB inverted data is read.
Bit Symbol
Symbol
Symbol
SVA0
SVA1
SVA2
SVA3
SVA4
SVA5
SVA6
ICDRT
Page 330 of 501
SAR
FS
Format select bit
Slave address 6 to 0
Address
Bit Name
00BDh
Address
00BEh
Function
0 : I
1 : Clock synchronous serial format
Set the different address from the other slave
devices w hich are connected to the I
When the 7 high-order bits of the first frame
transmitted after the starting condition match
the SVA0 to SVA6 bits in slave mode of the I
bus format, the MCU operates as a slave
device.
2
C bus format
16. Clock Synchronous Serial Interface
After Reset
Function
After Reset
00h
FFh
2
C bus.
2
C
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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