R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 359

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
16.3.3.3
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and
returns an acknowledge signal.
Figure 16.35 and Figure 16.36 show the Operation Timing in Master Receive Mode (I
The receive procedure and operation in master receive mode are shown below.
(1) After setting the TEND bit in the ICSR register to 0, switch from master transmit mode to master
(2) When performing the dummy-read of the ICDRR register and starting receive, output the receive clock
(3) The 1-frame data receive is completed and the RDRF bit in the ICSR register is set to 1 at the rise of the
(4) The continuous receive is enabled by reading the ICDRR register every time the RDRF bit is set to 1. If
(5) If the following frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1
(6) When the RDRF bit is set to 1 at the rise of the 9th clock of the receive clock, generate the stop
(7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register. And set the RCVD bit to 0
(8) Return to slave receive mode.
receive mode by setting the TRS bit in the ICCR1 register. And set the TDRE bit in the ICSR register to
0.
synchronizing with the internal clock and receive data. The master device outputs the level set by the
ACKBT bit in the ICIER register to the SDA pin at the 9th clock of the receive clock.
9th clock. At this time, when reading the ICDRR register, the received data can be read and the RDRF
bit is set to 0 simultaneously.
the 8th clock falls after reading the ICDRR register by the other processes while the RDRF bit is set to
1, the SCL signal is fixed “L” until the ICDRR register is read.
(disables the next receive operation) before reading the ICDRR register, the stop condition generation is
enabled after the following receive.
condition.
(maintain the following receive operation).
Master Receive Operation
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16. Clock Synchronous Serial Interface
2
C Bus Interface Mode).