R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 267

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.97
TSTART0 and TSTART1
bits in TRDSTR register
TRDGRD0 register
TRDGRB0 register
TRDSR1 register
TRDSR0 register
TRDSR0 register
TRDIOB0 output
TRDIOD0 output
TRDIOC0 output
IMFA bit in
IMFB bit in
UDF bit in
Count source
Value in TRDi register
0000h
m + 1
Operating Example of Complementary PWM Mode
CMD0, CMD1: Bits in TRDFCR register
i = 0 or 1
The above applies to the following conditions:
The OLS1 and OLS0 bits in the TRDFCR are set to 0 (initial output level “H”, active level “L” for normal-phase and counter-phase)
1
0
1
0
1
0
1
0
m
n
p
Initial output “H”
Initial output “H”
Page 245 of 501
Transfer (When the CMD1 to CMD0 bits are set to 11b)
Active level “L”
n + 1 - p
n + 1
m + 2 - p
n
n
p
m - p - n + 1
phase active level
(m - p - n + 1) × 2
Width of normal-
Set to 0 by a program
Set to 0 by a program
Dead
time
p
m: Setting Value in TRDGRA0 register
n: Setting Value in TRDGRB0 register
p: Setting Value in TRD0 register
Width of counter-phase active level
Transfer (When the CMD1 to CMD0 bits
Value in TRD0 register
are set to 10b)
n
Value in TRD1 register
Modify with a program
(n + 1 - p) × 2
n + 1 - p
Following data
Set to 0 by a program
FFFFh
Set to
14. Timers