R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 534

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Rev.
0.20
REVISION HISTORY
Jun 28, 2006
Date
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19.7 Notes on A/D Converter;
20. Flash Memory;
Table 20.1 Flash Memory Performance, Program and Erase Endurance;
20.2 Memory Map, on the 4th and 5th lines;
Figure 20.1 Flash Memory Block Diagram for R8C/22 Group revised.
Figure 20.2 Flash Memory Block Diagram for R8C/23 Group revised.
20.3 Functions to Prevent Rewriting of Flash Memory;
20.3.2 ROM Code Protect Function, on the 5th and 7th lines;
Figure 20.4 OFS Register revised.
20.4.2 EW1 Mode, on the 3rd line;
20.4.2.1 FMR00 Bit, on the 1st line;
20.4.2.16 FMR47 Bit revised.
Figure 20.5 FMR0 Register;
Figure 20.7 FMR4 Register;
Figure 20.8 Timing of Suspend Operation revised.
20.4.3.4 Program Command, on the 5th line;
Figure 20.13 Program Command (When Suspend Function Enabled)
added.
20.4.3.5 Block Erase, on the 11th line;
Figure 20.15 Block Erase Command (When Erase-Suspend Function
Enabled) revised.
Table 20.5 Status Register Bits, Value after Reset of SR7 (D7)
R8C/22 Group, R8C/23 Group Hardware Manual
“19.7 Precautions on A/D Converter” → “19.7 Notes on A/D Converter”
revised.
“20. Flash Memory Version” → “20. Flash Memory” revised.
“Program Area” → “Program ROM”
“Data Area” → “Data ROM” revised.
“(program ROM)” and “(data flash)” added.
“20.3 Functions to prevent Flash Memory from Rewriting” → “20.3
Functions to Prevent Rewriting of Flash Memory” revised.
“The ROM code ~ flash memory.” deleted.
“write 0 to the ROMCR bit” → “erase the block including the OFS
register” revised.
“Do not execute software command ~” → “Do not execute command
~” revised.
“(including suspend periods)” added.
NOTE6 added.
NOTES revised.
“The FMR00 bit is ~ completes.” → “When suspend function ~ auto-
programming completes.” revised.
“The block erase ~ program suspend.” → “Do not use ~ program-
suspend” revised.
“0” → “1” corrected.
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Description
Summary