R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 385
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 17.8
Timer RA Set to pulse width measurement mode
Timer RA Set the pulse width measurement level low
Timer RA Set the INT1/TRAIO pin to P1_5
Timer RA Set the count source (f1, f2, f8, fOCO)
Timer RA Set the Synch Break width
Hardware LIN Set the LIN operation to stop
Hardware LIN Set to slave mode
Hardware LIN Set the LIN operation to start
Hardware LIN Set the RXD0 input unmasking timing
Hardware LIN Set the register to enable interrupts
Bits TMOD0 to TMOD2 in the TRAMR register ← 011b
TEDGSEL bit in the TRAIOC register ← 0
TIOSEL bit in the TRAIOC register ← 1
TCK0 to 2 bits in the TRAMR register
TRAPRE register
TRA register
Example of Header Field Reception Flowchart (1)
LINE bit in the LINCR register ← 0
MST bit in the LINCR register ← 0
LINE bit in the LINCR register ← 1
(After Synch Break detection, or after Synch
Field measurement)
SBE bit in the LINCR register
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits BCIE, SBIE, SFIE in the LINCR register
Page 363 of 501
A
Set the count source and the TRA
and TRAPRE registers as suitable
for the Synch Break period.
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after detection of Synch
Break, the Synch Field signal too is
input to UART0.
17. Hardware LIN
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