R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 310
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 15.10
• Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit)
TI bit in UiC1
register
• Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits)
TI bit in UiC1
register
Transfer clock
TE bit in UiC1
register
TXEPT bit in
UiC0 register
IR bit SiTIC
register
Transfer clock
TE bit in UiC1
register
TXEPT bit in
UiC0 register
IR bit in SiTIC
register
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 1 (2 stop bits)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when transmit buffer is empty)
TXDi
TXDi
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 1 (parity enabled)
• STPS bit in UiMR register = 0 (1 stop bit)
• UiIRS bit in UiC1 register = 1 (an interrupt request is generated when transmit completes)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Transmit Timing in UART Mode
Write data to UiTB register
Write data to UiTB register
Transfer from UiTB register to UARTi transmit register
Transfer from UiTB register to UARTi transmit register
Start
Start
ST
ST
bit
bit
D0
D0
Page 288 of 501
D1
D1
TC
TC
D2
D2
Set to 0 when interrupt request is acknowledged, or set by a program
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7 D8
Parity
bit
P
Stop
Stop
bit
bit
SP
SP SP
Stop
bit
ST
D0
ST
Set to 0 when interrupt request is acknowledged, or set by a program
D0
D1
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
D1
D2
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 or 1
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 or 1
D2
D3
D3
D4
D4
D5
D5
D6
D7
D6
D7
P
Stop pulsing
because the TE bit is set to 0
D8
SP
SP SP
15. Serial Interface
ST
ST
D0
D1
D0
D1
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