R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 357

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
16.3.3.2
In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figure 16.33 and Figure 16.34 show the Operation Timing in Master Transmit Mode (I
The transmit procedure and operation in master transmit mode are shown below.
(1) Set the STOP bit in the ICSR register to 0 to reset it. And then set the ICE bit in the ICCR1 register to 1
(2) Read the BBSY bit in the ICCR2 register to confirm that the bus is free. Set the TRS and MST bits in
(3) After confirming that the TDRE bit in the ICSR register is set to 1 (data is transferred from the ICDRT
(4) When the transmit of 1-byte data is completed while the TDRE bit is set to 1, the TEND bit in the ICSR
(5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1.
(6) When writing the number of bytes to be transmitted to the ICDRT register, wait until the TEND bit is
(7) When the STOP bit in the ICSR register is set to 1, return to slave receive mode.
(transfer operation enabled). Set the WAIT and MLS bits in the ICMR register and set the CKS0 to
CKS3 bits in the ICCR1 register (initial setting).
the ICCR1 register to master transmit mode. The start condition is generated by writing 1 to the BBSY
bit and 0 to the SCP bit by the MOV instruction.
to ICDRS registers), write transmit data to the ICDRT register (data in which a slave address and R/W
are shown at the 1st byte). At this time, the TDRE bit is automatically set to 0 and data is transferred
from the ICDRT to ICDRS registers, the TDRE bit is set to 1 again.
register is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in the ICIER register,
and confirm that the slave is selected. Write the 2nd-byte data to the ICDRT register. Since the slave
device is not acknowledged when the ACKBR bit is set to 1, generate the stop condition. The stop
condition is generated by the writing 0 to the BBSY bit and 0 to the SCP bit by the MOV instruction.
The SCL signal is held “L” until data is available and the stop condition is generated.
set to 1 while the TDRE bit is set to 1. Or wait for NACK (the NACKF bit in the ICSR register is set to
1) from the receive device while the ACKE bit in the ICIER register is set to 1 (when the receive
acknowledge bit is set to 1, transfer is halted). And generate the stop condition before setting the TEND
and NACKF bits to 0.
Master Transmit Operation
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16. Clock Synchronous Serial Interface
2
C Bus Interface Mode).