R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 132

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
12.2
Figure 12.12
12.2.1
External Input Enable Register
b7 b6 b5 b4
NOTES:
1.
2.
The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN
register is set to 1 (enable). The edge polarity is selected using the INTiPL bit in the INTEN register and the
POL bit in the INTiIC register.
Inputs can be passed through a digital filter with three different sampling clocks.
The INT0 pin is shared with the pulse output forced cutoff of timer RD and shared with the external trigger
input of timer RB.
Figure 12.12 shows the INTEN Register. Figure 12.13 shows the INTF Register.
INT Interrupt
When setting the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling
edge).
The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to 12.7.4
Changing Interrupt Sources.
INTi Interrupt (i = 0 to 3)
b3 b2 b1 b0
INTEN Register
Bit Symbol
Symbol
INT0EN
INT1EN
INT2EN
INT3EN
INT0PL
INT1PL
INT2PL
INT3PL
INTEN
Page 110 of 501
_____
INT0
_____
INT0
_____
INT1
_____
INT1
_____
INT2
_____
INT2
_____
INT3
_____
INT3
input enable bit
input polarity select bit
input enable bit
input polarity select bit
input enable bit
input polarity select bit
input enable bit
input polarity select bit
Address
Bit Name
00F9h
(1,2)
(1,2)
(1,2)
(1,2)
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
After Reset
Function
00h
12. Interrupts
RW
RW
RW
RW
RW
RW
RW
RW
RW