R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 148
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
13.1
Table 13.2
NOTES:
Count Source
Count Operation
Period
Count Start Condition
Reset Condition of Watchdog
Timer
Count Stop Condition
Operation at the Time of
Underflow
The count source of the watchdog timer is the CPU clock when count source protection mode is disabled.
Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled).
1. The watchdog timer is reset when writing 00h to the WDTR register before writing FFh. The
2. The WDTON bit cannot be changed by a program. When setting the WDTON bit, write 0 to the bit 0
prescaler is reset after the MCU is reset. Some errors occur by the prescaler for the period of the
watchdog timer.
of the address 0FFFFh using a flash programmer.
Count Source Protection Mode Disabled
Item
Watchdog Timer Specifications (with Count Source Protection Mode Disabled)
Page 126 of 501
CPU clock
Decrement
Division ratio of prescaler(n) x count value of watchdog timer(32768)
n: 16 or 128 (selected by WDC7 bit in WDC register)
e.g.When the CPU clock is 16 MHz and prescaler is divided by 16, the
The WDTON bit
of watchdog timer after reset
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
• When the WDTON bit is set to 0 (watchdog timer starts automatically
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Stop and wait modes (inherit the count from the held value after exiting
modes)
• When the PM12 bit in the PM1 register is set to 0
• When the PM12 bit in the PM1 register is set to 1
The watchdog timer and prescaler stop after reset and the count
starts by writing to the WDTS register
after exiting)
The watchdog timer and prescaler start counting automatically after
reset
Watchdog timer reset (refer to 5.5 Watchdog Timer Reset)
reset)
Watchdog timer interrupt
period is approximately 32.8 ms
(2)
in the OFS register (0FFFFh) selects the operation
Specification
CPU clock
13. Watchdog Timer
(1)
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