R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 197
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.29
14.3.2
Table 14.22
i = 0 or 1
Input Capture Function
Output Compare Function Compare match with TRDi register
PWM Mode
Reset Synchronous PWM
Mode
Complementary PWM
Mode
PWM3 Mode
Function and Mode
The TRDGRCi register can be used as the buffer register of the TRDGRAi register, and the TRDGRDi register
can be used as the buffer register of the TRDGRBi register by the BFCi and BFDi bits in the TRDMR register.
Buffer operation depends on modes. Table 14.22 lists the Buffer Operation in Each Mode.
Figure 14.29 shows the Buffer Operation in Input Capture Function, and Figure 14.30 shows the Buffer
Operation in Output Compare Function.
• TRDGRAi buffer register: TRDGRCi register
• TRDGRBi buffer register: TRDGRDi register
i = 0 or 1
The above applies to the following conditions:
• The BFCi bit in the TRDMR register is set to 1. (The TRDGRCi register is used as the buffer register of
• The IOA2 to IOA0 bits in the TRDIORAi register are set to 100b (input capture at the falling edge).
Buffer Operation
the TRDGRAi register.)
Buffer Operation in Each Mode
Buffer Operation in Input Capture Function
TRDGRAi register
TRDGRCi register
TRDIOAi input
TRDi register
TRDIOAi input
(input capture signal)
Page 175 of 501
(buffer)
Input capture signal input
and TRDGRAi (TRDGRBi) register
Compare match withTRD0 register
and TRDGRA0 register
• Compare match with TRD0 register
• TRD1 register underflow
Compare match with TRD0 register
and TRDGRA0 register
and TRDGRA0 register
TRDGRCi
register
(buffer)
Transfer Timing
n-1
m
TRDGRAi
register
n
Transfer
Transfer
Transfer content in TRDGRAi
(TRDGRBi) register to buffer register
Transfer content in buffer register to
TRDGRAi (TRDGRBi) register
Transfer content in buffer register to
TRDGRAi (TRDGRBi) register
Transfer content in buffer register to
TRDGRB0, TRDGRA1 and
TRDGRB1 registers
Transfer content in buffer register to
TRDGRA0, TRDGRB0, TRDGRA1
and TRDGRB1 registers
m
n
Transfer Register
n+1
TRDi
14. Timers
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