R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 376

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
16.3.8
16.3.8.1
16.3.8.2
Set the IICSEL bit in the PMR register to 1 (select I
The following actions must be performed to use the I
Either of the following actions must be performed to use the I
•
•
(a) Use the MOV instruction to set bits MST and TRS.
(b) When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than the
(a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register
(b) In master receive mode, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
Transfer rate
Set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest
transfer rate of the other masters is set to 400 kbps, the I
223 kbps (= 400/1.18) or more.
Bits MST and TRS in the ICCR1 register setting
Notes on I
MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0
again.
before the rising edge of the 8th clock.
operation) to perform 1-byte communications.
Master Receive Mode
Multimaster Operation
Page 354 of 501
2
C Bus Interface
2
C bus interface function) to use I
2
C bus interface in multimaster operation.
2
2
C-bus transfer rate in this MCU should be set to
C bus interface in master receive mode.
16. Clock Synchronous Serial Interface
2
C bus interface.