R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 277
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.105 Registers TRDIER0 and TRDIER1 in PWM3 Mode
Figure 14.106 TRD0 Register in PWM3 Mode
Timer RD Interrupt Enable Register i (i = 0 or 1)
Timer RD Counter 0
(b15)
b7 b6 b5 b4
b7
NOTES:
1.
2.
Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
The TRD1 register is not used in PWM3 mode.
b3 b2
b1 b0
(b8)
b0
b7
Count a count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.
(1,2)
Bit Symbol
TRDIER0
TRDIER1
(b7 - b5)
Symbol
IMIEA
IMIEB
IMIEC
IMIED
OVIE
Page 255 of 501
—
Input capture/compare match
interrupt enable bit A
Input capture/compare match
interrupt enable bit B
Input capture/compare match
interrupt enable bit C
Input capture/compare match
interrupt enable bit D
Overflow /underflow interrupt enable
bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
b0
Symbol
TRD0
Address
Bit Name
0144h
0154h
Function
0147h-0146h
Address
0 : Disable an interrupt (IMIA) by the
1 : Enable an interrupt (IMIA) by the
0 : Disable an interrupt (IMIB) by the
1 : Enable an interrupt (IMIB) by the
0 : Disable an interrupt (IMIC) by the
1 : Enable an interrupt (IMIC) by the
0 : Disable an interrupt (IMID) by the
1 : Enable an interrupt (IMID) by the
0 : Disable an interrupt (OVI) by the
1 : Enable an interrupt (OVI) by the
IMFA bit
IMFA bit
IMFB bit
IMFB bit
IMFC bit
IMFC bit
IMFD bit
IMFD bit
OVF bit
OVF bit
After Reset
11100000b
11100000b
Function
0000h to FFFFh
Setting Range
After Reset
0000h
14. Timers
RW
RW
RW
RW
RW
RW
—
RW
RW
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