R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 209

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.39
Timer RD I/O Control Register Ai (i = 0 or 1)
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
1
When selecting 1 (The TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi
bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi
register.
When selecting 1 (The TRDGRDi register is used as a buffer register of TRDGRBi register) for this bit by the BFDi bit
in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi
register.
The IOA3 bit in the only TRDIORA0 register is enabled. Set to the IOA3 bit in the TRDIORA1 to 1.
The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function).
b3 b2
1
Registers TRDIORA0 to TRDIORA1 in Input Capture Function
b1 b0
TRDIORA0
TRDIORA1
Bit Symbol
Symbol
Page 187 of 501
IOA0
IOA1
IOA2
IOA3
IOB0
IOB1
IOB2
(b7)
—
TRDGRA control bit
TRDGRA mode selection bit
Input capture input sw itch
bit
TRDGRB control bit
TRDGRB mode selection bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
(3,4)
Address
Bit Name
0141h
0151h
(2)
(1)
b1 b0
0 0 : Input capture to the TRDGRAi register
0 1 : Input capture to the TRDGRAi register
1 0 : Input capture to the TRDGRAi register
1 1 : Do not set
b5 b4
0 0 : Input capture to the TRDGRBi register
0 1 : Input capture to the TRDGRBi register
1 0 : Input capture to the TRDGRBi register
1 1 : Do not set
Set to 1 (input capture) in the input capture
function
0 : fOCO128 Signal
1 : TRDIOA0 pin
Set to 1 (input capture) in the input capture
function
at the rising edge
at the falling edge
at both edges
at the rising edge
at the falling edge
at both edges
After Reset
10001000b
10001000b
Function
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
—