R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 356
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.32
16.3.3
16.3.3.1
(1) I
(2) I
Explanation of symbols
S
SLA
R/W
A
DATA : Transmit / receive data
P
(a) I
(b) I
Setting the FS bit in the SAR register to 0 communicates in I
Figure 16.32 shows the I
bits.
2
2
C bus Format
C bus timing
: Start condition
: Slave address
: Indicates the direction of data transmit/receive
2
2
: Acknowledge
: Stop condition
The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.
C bus format (FS = 0)
C bus format (when start condition is retransmitted, FS = 0)
The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”.
Data is transmitted from the slave device to the master device when R/W value is 1 and from the master device to the slave device when
The receive device sets the SDA signal to “L”.
R/W value is 0.
SDA
SCL
I
S
S
1
1
2
C Bus Interface Mode
I
S
I
2
2
C Bus Format and Bus Timing
C Bus Format
SLA
SLA
7
7
1 to 7
SLA
1
1
Page 334 of 501
R/W
R/W
8
2
1
1
R/W
C Bus Format and Bus Timing. The 1st frame following start condition consists of 8
A
1
A
1
9
A
DATA
DATA
n
n1
1 to 7
m1
DATA
8
A
1
m
A/A
1
9
A
S
1
2
A/A
C bus format.
1 to 7
1
SLA
7
P
1
DATA
1
8
16. Clock Synchronous Serial Interface
Transfer bit numbers (n = 1 to 8)
Transfer frame numbers (m = from 1)
R/W
1
9
A
Upper: Transfer bit numbers (n1, n2 = 1 to 8)
Lower: Transfer frame numbers (m1, m2 = from 1 )
A
1
P
DATA
n2
m2
A/A
1
P
1
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