R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 283

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
14.3.12 Notes on Timer RD
Table 14.36
When the CSELi bit is set to 1, set the TSTARTi bit to 0 and the count
stops.
When the CSELi bit is set to 0, the count stops at compare match of
registers TRDi and TRDGRAi.
14.3.12.1 TRDSTR Register
14.3.12.2 TRDi Register (i = 0 or 1)
14.3.12.3 TRDSRi Register (i = 0 or 1)
When writing the value to the TRDSRi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
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•
•
•
•
Set the TRDSTR register using the MOV instruction.
When the CSELi (i = 0 or 1) is set to 0 (the count stops at compare match of registers TRDi and
TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is
written to the TSTARTi bit.
Therefore, set the TSTARTi bit to 0 to change other bits without changing the TSTARTi bit when the
CSELi bit is set to 0.
To stop counting by a program, set the TSTARTi bit to 0 after setting the CSELi bit to 1. Although the
CSELi bit is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 instruction), the count cannot
be stopped.
Table 14.36 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops to use the TRDIOji
pin with the timer RD output.
When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register
is set to 1 (count starts), avoid to overlap with the timing to set the TRDi register to 0000h, and then write.
When the timing to set the TRDi register to 0000h overlaps with the timing to write the value to the TRDi
register, the value is not written and the TRDi register is set to 0000h.
- 001b (clear by the TRDi register at the compare match with the TRDGRAi register)
- 010b (clear by the TRDi register at the compare match with the TRDGRBi register.)
- 011b (synchronous clear)
- 101b (clear by the TRDi register at the compare match with the TRDGRCi register.)
- 110b (clear by the TRDi register at the compare match with the TRDGRDi register.)
When writing the value to the TRDi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
These precautions are applicable when selecting the following by the CCLR2 to CCLR0 bits in the
TRDCRi register.
Program Example
Program Example
TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops
Page 261 of 501
Count Stop
L1:
L1:
MOV.W
JMP.B
MOV.W
MOV.B
JMP.B
MOV.B
#XXXXh, TRD0
L1
TRD0,DATA
#XXh, TRDSR0
L1
TRDSR0,DATA
Hold the output level immediately before the
count stops.
Hold the output level after output changes by
compare match.
TRDIOji Pin Output when Count Stops
;Writing
;JMP.B
;Reading
;Writing
;JMP.B
;Reading
14. Timers