R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 145

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
13. Watchdog Timer
The watchdog timer is a function to detect when the program is out of control. To use the watchdog timer is
recommend for improving reliability of a system. The watchdog timer contains a 15-bit counter and can select count
source protection mode is enabled or disabled.
Table 13.1 lists the Count Source Protection Mode
Refer to 5.5 Watchdog Timer Reset for details of the watchdog timer reset.
Figure 13.1 shows the Block Diagram of Watchdog Timer, Figure 13.2 shows Registers OFS and WDC and Figure
13.3 shows Registers WDTR, WDTS, and CSPR.
Figure 13.1
Table 13.1
Count Source
Count Operation
Count Start Condition
Count Stop Condition
Reset Condition of Watchdog
Timer
Operation at the Time of
Underflow
CPU clock
Internal reset signal
NOTE:
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
Write to WDTR register
(“L” active)
Count Source Protection Mode
Block Diagram of Watchdog Timer
Item
Page 123 of 501
Prescaler
1/128
1/16
CPU clock
Decrement
Either of following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Stop mode, wait mode
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Watchdog timer interrupt or
watchdog timer reset
WDC7 = 1
WDC7 = 0
Count Source Protection
fOCO-S
Mode Disabled
CSPRO = 0
CSPRO = 1
Watchdog timer
Low-speed on-chip oscillator
clock
None
Watchdog timer reset
Count Source Protection
Set to
7FFFh
Mode Enabled
(1)
CSPRO: Bit in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
13. Watchdog Timer
PM12 = 0
Watchdog timer
interrupt request
PM12 = 1
Watchdog
timer reset