R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 285

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.110 Operation at Compare Match between Registers TRD0 and TRDGRA0 in
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
TRDSR0 register
Count value in TRD0
IMFA bit in
Setting value in
•
When the value in the TRDGRA0 register is assumed as m, the TRD0 register counts order of m - 1, m, m
+ 1, m, m - 1 when changing from increment to decrement.
When changing from m to m + 1, the IMFA bit is set to 1. Also, the CMD1 to CMD0 bits in the TRDFCR
register are set to 11b (complementary PWM mode, buffer data transferred by the compare match in the
TRD0 and TRDGRA0 registers), the content in the buffer register (TRDGRD0, TRDGRC1, TRDGRD1) is
transferred to the general register (TRDGRB0, TRDGRA1, TRDGRB1).
For the order of m + 1, m, m - 1 operation, the IMFA bit remains unchanged and data are not transferred to
the register such as the TRDGRA0 register.
register m
TRDGRA0
Complementary PWM Mode
register
1
0
Set to 0 by a program
Page 263 of 501
Transferred from
buffer register
m + 1
No change
Not transferred from buffer register
When the CMD1 to CMD0 bits in the
TRDFCR register are set to 11b.
(Transfer from the buffer register to the
general register at the compare match
of the TRD0 register and TRDGRA0
register)
14. Timers