R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 146
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 13.2
Option Function Select Register
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
b7 b6 b5 b4
1.
2.
3.
0 0
1 1
The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
To use the pow er-on reset, set the LVD1ON bit to 0 (voltage monitor 1 reset enabled after reset).
If the block including the OFS register is erased, FFh is set to the OFS register.
b3 b2 b1 b0
Registers OFS and WDC
1
Bit Symbol
Bit Symbol
CSPROINI
ROMCP1
LVD1ON
WDTON
ROMCR
(b5-b4)
(b4-b0)
Symbol
Symbol
WDC7
WDC
Page 124 of 501
OFS
(b1)
(b5)
(b6)
—
—
—
—
—
Watchdog timer start
select bit
Reserved bit
ROM code protect
disabled bit
ROM code protect bit
Reserved bits
Voltage detection circuit
start bit
Count source protect
mode after reset select
bit
High-order bits of w atchdog timer
Reserved bits
Reserved bits
Prescaler select bit
(1)
(2)
Address
Bit Name
Address
Bit Name
0FFFFh
000Fh
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
Set to 1
0 : ROM code protect disabled
1 : ROMCP1 enabled
0 : ROM code protect enabled
1 : ROM code protect disabled
Set to 1
0 : Voltage monitor 1 reset enabled after reset
1 : Voltage monitor 1 reset disabled after reset
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
Set to 0.
When read, the content is undefined.
Set to 0
0 : Divide-by-16
1 : Divide-by-128
Before Shipment
After Reset
00X11111b
Function
Function
FFh
(3)
13. Watchdog Timer
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
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