R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 275

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.103 TRDCR0 Register in PWM3 Mode
Timer RD Control Register i (i = 0 or 1)
b7 b6 b5 b4
NOTES:
0 0 1
1.
2.
This bit is enabled w hen the TCK2 to TCK0 bits are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR
register is set to 1 (external clock input enabled).
The TRDCR1 register is not used in PWM3 mode.
b3 b2
b1 b0
Bit Symbol
TRDCR0
Symbol
CKEG0
CKEG1
CCLR0
CCLR1
CCLR2
TCK0
TCK1
TCK2
Page 253 of 501
Count source selection bit
External clock edge selection
bit
TRD0 counter clear selection bit
(1)
(2)
Address
Bit Name
0140h
b2 b1b0
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : Do not set
1 1 0 : fOCO40M
1 1 1 : Do not set
This bit is disabled in PWM3 mode.
Set to 001b (the TRD0 register clear at the
compare match w ith TRDGRA0 register) in
PWM3 mode.
After Reset
Function
00h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW