R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 389
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 389 of 551
- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 17.12
17.4.4
Timer RA
Timer RA
UART0 Complete transmission via UART0
Hardware LIN Clear the status flags
Hardware LIN Set the LIN operation to stop
Figure 17.12 shows an Example of Hardware LIN Communication Completion Flowchart.
Use the following timing for hardware LIN end processing:
•
•
If the hardware bus collision detection function is used
Perform hardware LIN end processing after checksum transmission completes.
If the bus collision detection function is not used
Perform hardware LIN end processing after header field transmission and reception complete.
Hardware LIN End Processing
Set the timer to stop counting
TSTART bit in TRACR register ← 0
Read the count status flag
TCSTF flag in TRACR register
Example of Hardware LIN Communication Completion Flowchart
(Bus collision detection, Synch Break detection, Synch
Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST register ← 1
LINE bit in the LINCR register ← 0
Page 367 of 501
TCSTF = 0 ?
YES
NO
Set the timer to stop counting.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the
TCSTF flag is set to 1.
When the bus collision detection
function is not used, end
processing for the UART0
transmission is not required.
After clearing hardware LIN
status flag, stop the
hardware LIN operation.
17. Hardware LIN
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