R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 91

IC R8C/23 MCU FLASH 48-LQFP

R5F21238DFP#U0

Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Datasheets

Specifications of R5F21238DFP#U0

Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
8.
8.1
Figure 8.1
Figure 8.2
Table 8.1
Single-chip mode
Processor Mode Register 0
Processor Mode Register 1
Single-chip mode can be selected as processor mode.
Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1
Register.
b7 b6 b5 b4 b3 b2
NOTE:
b7 b6 b5 b4 b3 b2
NOTES :
0
Processor Mode
1.
1.
2.
Processor Mode
Processor Modes
Set the PRC1 bit in the PRCR register to 1 (enables w riting) before rew riting to the PM0 register.
Set the PRC1 bit in the PRCR register to 1 (enables w riting) before rew riting to the PM1 register.
The PM12 bit is set to 1 by a program (it remains unchanged even if it is set to 0).
When the CSPRO bit in the CSPR register is set to 1 (selects count source protect mode), the PM12 bit is
automatically set to 1.
0
PM0 Register
PM1 Register
Features of Processor Mode
b1 b0
b1 b0
0 0
0 0
Bit Symbol
Bit Symbol
(b2-b0)
(b7-b4)
(b1-b0)
(b6-b3)
Symbol
Symbol
PM03
PM12
Page 69 of 501
PM0
PM1
(b7)
(1)
(1)
SFR, internal RAM, internal ROM All pins are I/O ports or peripheral
Reserved bits
Softw are reset bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Reserved bits
WDT interrupt/reset sw itch bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Reserved bit
Accessible Areas
Address
Bit Name
Address
Bit Name
0004h
0005h
Set to 0
The MCU is reset w hen this bit is set to 1.
When read, its content is 0.
Set to 0
0 : Watchdog timer interrupt
1 : Watchdog timer reset
Set to 0
function I/O pins
Pins Assignable as I/O Port Pins
After Reset
After Reset
Function
Function
00h
00h
(2)
8. Processor Mode
RW
RW
RW
RW
RW
RW
RW

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