R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 280
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.108 Operating Example of PWM3 Mode
TRDGRA0 register
TRDGRC0 register
TRDSTR register
TRDSTR register
TRDSR0 register
TRDSR0 register
TRDIOA0 output
TRDIOB0 output
TSTART0 bit in
CSEL0 bit in
IMFA bit in
IMFB bit in
Count source
j = either A or B
The above applies to the following conditions:
• Both the TOA0 and TOB0 bits in the TRDOCR register are set to 0 (initial output level “L”, output “H” by the compare match in the
• The BFC0 bit in the TRDMR register is set to 1 (the TRDGRC0 register is used as the buffer register of the TRDGRA0 register).
TRDGRj1 register, output “L” by the compare match in the TRDGRj0 register)
Value in TRD0 register
FFFFh
0000h
m
n
p
q
1
0
1
0
1
0
1
0
Initial output “L”
Page 258 of 501
compare match in the
TRDGRA1 register
Output “H” by the
Set to 0 by a program
m
match in the TRDGRA0 register
Output “L” by the compare
m
Transfer from the buffer register
to general register
Set to 0 by a program
q + 1
Transfer
p + 1
n + 1
Set to 0 by a program
p - q
m + 1
Set to 0 by a program
m: Setting value in TRDGRA0 register
n: Setting value in TRDGRA1 register
p: Setting value in TRDGRB0 register
q: Setting value in TRDGRB1 register
m
Following data
Transfer from the buffer register
m - n
to general register
Set to 0 by a program
Count stop
Transfer
14. Timers
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