R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 374

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.48
ICSR register
ICSR register
ICCR1 register
ICSR Register
Write transmit data to ICDRT register
Write transmit data to ICDRT register
Read TDRE bit in ICSR register
Read TEND bit in ICSR register
Dummy-read in ICDRR register
Example of Register Setting in Slave Transmit Mode (I
No
No
No
Slave transmit mode
TDRE = 1 ?
TEND = 1 ?
Last byte ?
Page 352 of 501
TEND bit ← 0
AAS bit ← 0
TDRE Bit ← 0
End
TRS bit ← 0
Yes
Yes
Yes
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(1) Set the AAS bit to 0
(2) Set the transmit data (except the last byte)
(3) Wait the ICDRT register is empty
(4) Set the transmit data of the last byte
(5) Wait the last byte is transmitted
(6) Set the TEND bit to 0
(7) Set to slave receive mode
(8) Dummy-read in the ICDRR register to release the
(9) Set the TDRE bit to 0
SCL signal
16. Clock Synchronous Serial Interface
2
C Bus Interface Mode)