R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 344
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
16.3
Table 16.5
NOTE:
Communication
Formats
I/O Pins
Transfer Clocks
Receive Error Detection • Detects overrun error (clock synchronous serial format)
Interrupt Sources
Select Functions
The I
Philips I
Table 16.5 lists a I
Figure 16.23 shows the External Circuit Connection Example of Pins SCL and SDA. Figures 16.24 to 16.31 show
the registers associated with the I
* I
1. The interrupt sources can use the only I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
2
I
C bus interface is the circuit which is used for a serial communication based on the data transfer format of the
2
2
C Bus Interface
C bus.
Item
I
2
C Bus Interface Specifications
2
C Bus Interface Specifications, Figure 16.22 shows a Block Diagram of I
Page 322 of 501
• I
• Clock synchronous serial format
SCL (I/O): Serial clock I/O pin
SDA (I/O): Serial data I/O pin
• When the MST bit in the ICCR1 register is set to 0
• When the MST bit in the ICCR1 register is set to 1
• I
• Clock synchronous serial format ...... 4 types
• I
• Clock synchronous serial format
2
- Selectable for master / slave device
- Continuous transmit / receive (since the shift register, transmit data register
- Start / stop conditions are automatically generated in master mode
- Automatic loading of acknowledge bit when transmit
- Bit synchronization / wait function (in master mode, the state of the SCL
- Direct drive of the SCL and SDA pins (N-channel open drain output) is
- Continuous transmit / receive (since the shift register, transmit data register
The external clock (input from the SCL pin)
The internal clock selected by the CKS0 to CKS3 bits in the ICCR1 register
(output from the SCL pin)
An overrun error occurs during receive. When the last bit of the following data
is received while the RDRF bit in the ICSR register is set to 1 (data in the
ICDRR register), the AL bit is set to 1.
2
Transmit data empty (including when slave address matches), transmit ends,
receive data full (including when slave address matches), arbitration lost,
NACK detection and stop condition detection.
Transmit data empty, transmit ends, receive data full and overrun error
2
- Selectable for the output level of the acknowledge signal when receive
- Selectable for the MSB-first or LSB-first to the data transfer direction
C bus format
C bus format .................................. 6 types
C bus format
and receive data register are independent)
signal is monitored per bit and the timing is synchronized automatically. If
the transfer is not possible yet, stand by to set the SCL signal to “L”.
enabled
and receive data register are independent)
2
C bus interface.
2
C bus interface interrupt vector table.
Specification
16. Clock Synchronous Serial Interface
(1)
(1)
2
C bus Interface and
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