R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 126

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Table 12.3
ILVL2 to ILVL0 Bits
12.1.6.1
12.1.6.2
12.1.6.3
000b
001b
010b
100b
101b
011b
110b
111b
The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (enabled) enables the maskable
interrupt. Setting the I flag to 0 (disabled) disables all maskable interrupts.
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (=
interrupt not requested).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
Operations of the IR bit vary by Timer RD interrupt, clock synchronous serial I/O interrupt with chip select or
I
For details, refer to 12.6 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts
and I
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 12.3 lists the Settings of Interrupt Priority Levels and Table 12.4 lists the Interrupt Priority Levels
Enabled by IPL.
The following are conditions under which an interrupt is acknowledged:
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. They do not affect one another.
2
C bus interface interrupt.
•
•
•
I flag = 1
IR bit = 1
Interrupt priority level > IPL
2
C bus Interface Interrupts (Interrupts with Multiple Interrupt Request Sources).
Settings of Interrupt Priority
Levels
I Flag
IR Bit
Bits ILVL2 to ILVL0 and IPL
Level 3
Level 6
Level 7
Level 0 (interrupt disabled)
Level 1
Level 2
Level 4
Level 5
Interrupt Priority Level
Page 104 of 501
Priority Order
High
Low
−
Table 12.4
000b
001b
010b
100b
101b
011b
110b
111b
IPL
IPL
Interrupt Priority Levels Enabled by
Interrupt level 1 and above
Interrupt level 2 and above
Interrupt level 3 and above
Interrupt level 4 and above
Interrupt level 5 and above
Interrupt level 6 and above
Interrupt level 7 and above
All maskable interrupts are disabled
Enabled Interrupt Priority Levels
12. Interrupts