R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 123

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 12.3
12.1.6
Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
1.
2.
The following describes enable/disable the maskable interrupts and set the priority order to acknowledge. The
contents explained does not apply to the nonmaskable interrupts.
Use the I flag in the FLG register, IPL and the ILVL2 to ILVL0 bits in each interrupt control register to enable/
disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt
control register.
Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRD0IC, TRD1IC, SSUIC, and
IICIC and Figure 12.5 shows the Registers INT0IC to INT3IC.
Only 0 can be w ritten to the IR bit. Do not w rite 1.
Rew rite the interrupt control register, rew rite it w hen the interrupt request w hich is applicable for its register is not
generated. Refer to 12.7.5 Changing Interrupt Control Register Contents.
Interrupt Control
Interrupt Control Register
Bit Symbol
C01ERRIC
C01WKIC
C0RECIC
C0TRMIC
(b7-b4)
Symbol
TRAIC
TREIC
KUPIC
S0TIC
S0RIC
S1TIC
S1RIC
TRBIC
ILVL0
ILVL1
ILVL2
Page 101 of 501
ADIC
—
IR
(2)
Interrupt priority level select bits
Interrupt request bit
Nothing is assigned. If necessary, set to 0.
When read, the content is indeterminate.
Address
Bit Name
004Ah
0043h
0044h
0045h
0046h
004Dh
004Eh
0051h
0052h
0053h
0054h
0056h
0058h
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Requests no interrupt
1 : Requests interrupt
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
After Reset
Function
12. Interrupts
RW
RW
RW
RW
RW
—
(1)