R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 199
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.31
14.3.3
• The IOA2 to IOA0 bits in the TRDIORA0 register are set to 100b.
• The CMD1 to CMD0 bits in the TRDFCR register are set to 00b.
The above applies to the following conditions:
• The SYNC bit in the TRDMR register is set to 1 (synchronous operation).
• The CCLR2 to CCLR0 bits in the TRDCR0 register are set to 001b (set the TRD0 register to 0000h in input capture).
The PWM 3 bit in the TRDFCR register is set to 1.
The CCLR2 to CCLR0 bits in the TRDCR1 register are set to 011b.
(Set the TRD1 register to 0000h synchronizing with the TRD0 register.)
The TRD1 register is synchronized with the TRD0 register.
TRDIOA0 input
• Synchronous preset
• Synchronous clear
TRD0 register
TRD1 register
When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both
the TRD0 and TRD1 registers after writing to the TRDi register.
When the SYNC bit in the TRDMR register is set to 1 and the CCLR2 to CCLR0 bits in the TRDCRi
register are set to 011b (synchronous clear), and the TRD0 register is set to 0000h at the same time as the
TRD1 register is set to 0000h.
Also, when the SYNC bit in the TRDMR register is set to 1 and the CCLR2 to CCLR0 bits in the TRDCRi
register are set to 011b (synchronous clear), and the TRD1 register is set to 0000h at the same time as the
TRD0 register is set to 0000h.
Synchronous Operation
Value in
Value in
Synchronous Operation
n
n
Page 177 of 501
n writing
n is set
n is set
Set to 0000h with TRD0 register
Set to 0000h by input capture
(Input capture at the rising edge of the TRDIOA0 input)
14. Timers
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