R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 100

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 10.8
CAN0 Clock Select Register
b7 b6 b5 b4 b3 b2 b1
NOTES:
1.
2.
3.
Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the CCLKR register.
Set to the CCLK2, CCLK1, CCLK0 bits, only w hen the Reset bit in the C0CTLR register is 1 (reset/initialization mode).
When set the CCLK3 bit to 1 (CAN0 CPU interface operating), set to the Sleep bit in the C0CTLR register to 1 before
setting the CCLK3 bit.
CCLKR Register
b0
Bit Symbol
(b7-b4)
Symbol
CCLKR
CCLK0
CCLK1
CCLK2
CCLK3
Page 78 of 501
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(1)
CAN0 clock select bits
CAN0 CPU interface sleep bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Address
Bit Name
135Fh
(2)
(3)
b2 b1 b0
0 0 0 : No division
0 0 1 : Divide-by-2 mode
0 1 0 : Divide-by-4 mode
0 1 1 : Divide-by-8 mode
1 0 0 : Divide-by-16 mode
1 0 1 :
1 1 0 :
1 1 1 :
0 : CAN0 CPU interface operating
1 : CAN0 CPU interface in sleep
Do not set
After Reset
Function
00h
10. Clock Generation Circuit
RW
RW
RW
RW
RW
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