R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 113

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
10.5
Table 10.5
10.5.1
Oscillation Stop Detection Clock and
Frequency Bandwidth
Enabled Condition for Oscillation Stop
Detection Function
Operation at Oscillation Stop Detection
The oscillation stop detection function is a function to detect the stop of the XIN clock oscillating circuit. The
oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register.
Table 10.5 lists the Specifications of Oscillation Stop Detection Function.
When the XIN clock is the CPU clock source and the OCD1 to OCD0 bits are set to 11b, the system is placed in
the following state if the XIN clock stops.
Oscillation Stop Detection Function
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OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)
OCD3 bit in OCD register = 1 (XIN clock stops)
CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)
Oscillation stop detection interrupt request is generated
The oscillation stop detection interrupt shares the vector with the voltage monitor 2 interrupt and the
watchdog timer interrupt. When using the oscillation stop detection interrupt and watchdog timer interrupt,
the interrupt cause needs to be determined.
Table 10.6 lists the Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage
Monitor 1, and Voltage Monitor 2 Interrupts.
Figure 10.15 shows an Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog
Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt.
When the XIN clock is re-oscillated after oscillation stop, switch the XIN clock to the clock source of the
CPU clock and peripheral functions by a program.
Figure 10.14 shows the Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to
XIN Clock.
To enter wait mode while using the oscillation stop detection function, set the CM02 bit to 0 (peripheral
function clock does not stop in wait mode).
Since the oscillation stop detection function is a function preparing to stop the XIN clock by the external
cause, set the OCD1 to OCD0 bits to 00b when the XIN clock stops or oscillates in the program, that is stop
mode is selected or the CM05 bit is changed.
This function cannot be used when the XIN clock frequency is less than 2 MHz. Set the OCD1 to OCD0
bits to 00b.
When using the low-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral
functions after detecting the oscillation stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on-
chip oscillator selected) and the OCD1 to OCD0 bits to 11b.
When using the high-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral
functions after detecting the oscillation stop, set the FRA00 bit to 1 (high-speed on-chip oscillator on) and
the FRA01 bit to 1 (high-speed on-chip oscillator selected) and the OCD1 to OCD0 bits to 11b.
How to Use Oscillation Stop Detection Function
Specifications of Oscillation Stop Detection Function
Item
Page 91 of 501
Oscillation stop detection interrupt is generated
f(XIN) ≥ 2 MHz
Set OCD1 to OCD0 bits to 11b
Specification
10. Clock Generation Circuit