R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 421
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
19. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. The analog input shares the pins with P0_0 to P0_7, P1_0 to P1_3. Therefore, when using these pins, ensure
the corresponding port direction bits are set to 0 (input mode).
When not using the A/D converter, set the VCUT bit in the ADCON1 register to 0 (Vref unconnected), so that no
current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The result of A/D conversion is stored in the AD register.
Table 19.1 lists the Performance of A/D Converter. Figure 19.1 shows the Block Diagram of A/D Converter. Figure
19.2 and Figure 19.3 show the A/D converter-related registers.
Table 19.1
NOTES:
A/D Conversion Method
Analog Input Voltage
Operating Clock φAD
Resolution
Absolute Accuracy
Operating Mode
Analog Input Pin
A/D Conversion Start Condition • Software trigger
Conversion Rate Per Pin
1. Analog input voltage does not depend on use of sample and hold function.
2. The frequency of φAD must be 10 MHz or below.
3. In repeat mode, only 8-bit mode can be used.
When analog input voltage exceeds reference voltage, A/D conversion result is 3FFh in 10-bit
mode, FFh in 8-bit mode.
Without sample and hold function, the φAD frequency should be 250 kHz or above.
With the sample and hold function, the φAD frequency should be 1 MHz or above.
Item
Performance of A/D Converter
(1)
(2)
Page 399 of 501
Successive approximation (with capacitive coupling amplifier)
0 V to AVCC
4.2 V ≤ AVCC ≤ 5.5 V f1, f2, f4, fOCO-F
2.7 V ≤ AVCC < 4.2 V f2, f4, fOCO-F
8 bit or 10 bit is selectable
AVCC = Vref = 5 V, φAD = 10MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±3 LSB
AVCC = Vref = 3.3 V, φAD = 10MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
One-shot and repeat modes
12 pins (AN0 to AN11)
• Capture
• Without sample and hold function
• With sample and hold function
Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts)
Timer RD interrupt request is generated while the ADST bit is set to 1
8-bit resolution: 49φAD cycles, 10-bit resolution: 59φAD cycles
8-bit resolution: 28φAD cycles, 10-bit resolution: 33φAD cycles
(3)
Performance
19. A/D Converter
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