R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 305
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 15.7
• Example of transmit timing (when internal clock is selected)
• Example of receive timing (when external clock is selected)
The above applies under the following settings:
The following conditions are met when “H” is applied to the CLK0 pin before receiving data:
fEXT: Frequency of external clock
The above applies under the following settings:
TE bit in U0C1
register
TI bit in U0C1
register
CLK0
TXD0
TXEPT bit in
U0C0 register
IR bit in S0TIC
register
RE bit in U0C1
register
TE bit in U0C1
register
TI bit in U0C1
register
CLK0
RXD0
RI bit in U0C1
register
IR bit in S0RIC
register
• CKDIR bit in U0MR register = 1 (external clock)
• CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
• TE bit in U0C1 register = 1 (enables transmit)
• RE bit in U0C1 register = 1 (enables receive)
• Write dummy data to the U0TB register
• CKDIR bit in U0MR register = 0 (internal clock)
• CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
• U0IRS bit in U0C1 register = 0 (an interrupt request is generated when the transmit buffer is empty)
Transfer clock
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode
Set data in U0TB register
Write dummy data to U0TB register
Transfer from U0TB register to UART0 transmit register
Transfer from UART0 receive register to
Transfer from U0TB register to UART0 transmit register
D0
D0
D1
D1
Page 283 of 501
D2
D2
TCLK
D3
D3
1/fEXT
U0RB register
D4
D4
TC
Receive data is taken in
D5
D5
D6
D6
Set to 0 when interrupt request is acknowledged, or set by a program
D7
D7
D0 D1
Set to 0 when interrupt request is acknowledged, or set by a program
D0 D1
D2
D3
D2
Read out from U0RB register
D3
D4
TC = TCLK = 2(n+1)/fi
D5
D4
fi: Frequency of UiBRG count source (f1, f8, f32)
n: Setting value to UiBRG register
D6
D5
D7
Stop pulsing because the TE bit is set to 0
D0 D1
D2
D3
D4
15. Serial Interface
D5
D6
D7
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